Current wireless technology trends increasingly favor smaller devices, implementations of which generally require some digital components. For example, class D and class F amplifiers are switching amplifiers that provide a digital amplification option for analog inputs. These amplifiers require harmonic tuning networks, which are bulky, and are therefore difficult to integrate on a digital chip. Further, such tuning networks generally must be operated at frequencies below 300 MHz due to parasitic limitations. Thus, such switching amplifiers are problematic for wireless telecommunication frequency applications, which are generally between 900 MHz and 5.8 GHz.
Another option is the use of digital radio frequency (RF) power amplifiers. In this case, the input is digital, and thus no analog matching network is used. The clock frequency of the digital signal sets the carrier radio frequency by toggling between “0” and “1” at a desired speed. Conventional digital RF power amplifiers, however, are inefficient. Further, the efficiency of such digital RF power amplifiers cannot be controlled with conventional biasing and/or harmonic matching techniques. Thus, there remains a need for alternative solutions that are compatible with small chip designs and have improved efficiency.